You can run the system control code with the other nonperformance-critical DSP algorithms on a Nios ® II embedded processor. Then, you can use Intel's DSP IP or develop your own custom instructions to accelerate those tasks in the FPGA. In this flow, you first profile C code and identify the functions that are the most performance critical.
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You can combine a software design flow with hardware acceleration.
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You can then use either on-chip RAM or an external memory device to download these software designs to an FPGA.Įmbedded processors and hardware acceleration offer the flexibility, performance, and cost effectiveness in a development flow that is familiar to software developers.
Intel provides the Nios ® II EDS development tools for compiling, debugging, assembling, and linking software designs. Intel FPGAs with embedded processors support a software-based design flow. The flexibility of programmable logic and soft IP allows you to quickly adapt your designs to new standards without waiting for long lead times usually associated with DSP processors. You can easily port the IP to new FPGA families, leading to higher performance and lower cost. You can parameterize Intel DSP IP for the most efficient hardware implementation and to provide maximum flexibility. Intel offers many IPs for DSP design on FPGAs. You can implement hardware accelerator blocks with parameterizable IP functions or from scratch using HDL. DSP processors have predefined hardware accelerator blocks, but FPGAs can implement hardware accelerators for each application, allowing the best achievable performance from hardware acceleration. FPGA devices provide a flexible platform to accelerate performance-critical functions in hardware because of the configurability of the device’s logic resources. Soft embedded processors in FPGAs provide access to custom instructions such as the MUL instruction in Nios ® II processors that can perform a multiplication operation in two clock cycles using hardware multipliers. Off-the-shelf DSP processors make compromises between size and performance when they choose the number of data buses on the chip, potentially limiting performance. You can use multimaster buses to define as many buses and as much performance as needed for a particular application. The Nios ® II processor supports a user-determinable multimaster bus architecture that optimizes the bus bandwidth and removes potential bottlenecks found in DSP processors.
You can implement soft core processors such as the Nios ® II embedded processor in FPGAs and add multiple system peripherals. Intel devices provide a choice between embedded soft core processors and embedded hard core processors. You can implement the system’s software components in the embedded processors and implement the hardware components in the FPGA's general logic resources. The embedded memory in FPGAs meets these requirements and also eliminates the need for external memory devices in some cases.Įmbedded processors in FPGAs provide versatile system integration because of flexible partitioning of the system between hardware and software. Many DSP applications use external memory devices to manage large amounts of data processing. One determining factor of the overall DSP bandwidth is the multiplier bandwidth, therefore the overall DSP bandwidth of FPGAs can be much higher using FPGAs than with DSP processors. Generally, Intel FPGAs offer much more multiplier bandwidth than DSP processors, which only offer a limited number of multipliers. The embedded DSP blocks provide functionality such as addition, subtraction, and multiplication, which are common arithmetic operations in DSP functions. Embedded silicon features such as embedded memory, DSP blocks, and embedded processors are ideally suited for implementing DSP functions such as finite impulse response (FIR) filters, fast Fourier transforms (FFTs), correlators, equalizers, encoders, and decoders. High-density FPGAs incorporate embedded silicon features that can implement complete systems inside an FPGA, creating a system on a programmable chip (SOPC) implementation. Thus, the same FPGA can implement a DSL router, a DSL modem, a JPEG encoder, a digital broadcast system, or a backplane switch fabric interface. You can use a suitable hardware description language (HDL) such as VHDL or Verilog HDL to implement any hardware design. You can configure FPGAs to operate in different modes corresponding to your required functionality.
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